The work helps to increase the understanding of the potential to scale CFETs for logic and SRAM applications. The researchers also will describe a nanoribbon “depopulation” methodology for when unequal numbers of NMOS and PMOS channels are required. In addition Intel has include backside power delivery, an idea that was also proposed by IMEC and that is now part of the Intel roadmap for delivery in its Intel 20A – or 20 angstrom – manufacturing process.
The devices also featured vertically stacked dual-S/D epitaxy dual metal work function gate stacks connecting the n- and p-transistors. The Intel team are due to describe a industry first – fully functioning inverter test circuits in CFET – built at a 60nm gate pitch. IMEC has previously made the point that standard cell area is mainly dependent on access to transistor terminals and that CFETs can simplify this. But it also means that CMOS logic circuitry can be designed more efficiently. The CFET provides the obvious benefit of two transistors occupying the space of one in a GAA, FinFET or planar architecture.
